Microbump Lithography for 3d Stacking Applications

3D packaging solutions are expected to play an important role in delivering improved performance, smaller form factors, and reduce costs for advanced semiconductor devices. The physical stacking of die-to-die or die-to-wafer requires high interconnect density. Aggressive scaling of microbump diameters and pitch is essential to meet these interconnect requirements. Maintaining process control for microbump lithography is challenging due to the small bump diameters and high aspect ratios. Since lithography is one of the important process sequences affecting final product yield, it is especially important to control the photoresist side wall profile and critical dimensions (CD). This paper will evaluate the use of stepper technology to meet the lithographic process control requirements for microbump applications. Silicon wafers with Cu seed layer were used as a test vehicle to closely match the features of an advanced microbump product. The photoresist is a positive acting material coated to a thickness of 13 m. Microbumps with a CD of 3.5 m on a 10 m pitch were exposed on the test wafers using a 1X stepper. CD metrology at the bottom and top of the photoresist was performed using a top down CD-SEM. The photoresist profile results were confirmed by cross sectional SEM analysis. A process latitude evaluation was performed by varying the exposure dose and focus offset for each field across a wafer. The lithographic process window was obtained by analyzing the resulting focus versus exposure matrix. The optimal lithography conditions were determined from this process window. These conditions were then monitored using CD metrology in a fabrication environment. The stability of the process was demonstrated over an extended period using the top CD for statistical process control (SPC). The experimental photoresist profiles through focus and exposure were also compared with optical lithographic simulations using Prolith modeling software by KLATencore. The simulation results were validated by matching the experimental process window at the same process conditions. Photoresist simulation was then used to evaluate conditions beyond the experimental process such as smaller CD and pitch. The effect of photomask biasing to enhance process latitude was also investigated. The experimental and modeled CD and side wall profile demonstrate a robust lithographic process for next generation microbump applications.